CASUS Institute Seminar, Jens Domke, Leader Supercomputing Performance Research Team (SuPeR), RIKEN Center for Computational Science (R-CCS), Kobe, Japan
Abstract of the talk// Over the last three decades, innovations in the memory subsystem were primarily targeted at overcoming the data movement bottleneck. In this talk, Jens focuses on a specific market trend in memory technology: 3D-stacked memory and caches. He investigates with his team the impact of extending the on-chip memory capabilities in future HPC-focused processors, particularly by 3D-stacked SRAM.
First, he proposes a method oblivious to the memory subsystem to gauge the upper-bound in performance improvements when data movement costs are eliminated. Then, using the gem5 simulator, the team modeled two variants of LARC, a processor fabricated in 1.5 nm and enriched with high-capacity 3D-stacked cache. With a volume of experiments involving a board set of proxy-applications and benchmarks, the aim is to reveal where HPC CPU performance could be circa 2028.
Jens Domke will be talking live in Görlitz. However, as the event is organized in a hybrid format that includes a videoconferencing tool by Zoom Inc., people interested in the topic have the chance to join the talk remotely. Please ask for the videoconferencing details via firstname.lastname@example.org.